1. Field of Invention
This invention relates to a leadless semiconductor package. More particularly, the present invention is related to a leadless semiconductor package with high reliability of the attachment of the encapsulation to the leadless lead-frame.
2. Related Art
Integrated circuits (chip) packaging technology is becoming a limiting factor for the development in packaged integrated circuits of higher performance. Semiconductor package designers are struggling to keep pace with the increase in pin count, size limitations, low profile, and other evolving requirements for packaging and mounting integrated circuits. Nowadays, ball grid array package (BGA) and chip scale package (CSP) are wildly applied to chip package with high I/Os and assembly package for thermal enhance integrated circuits.
However, assembly package with lead frame possesses great marketing for that it can provide low-cost solutions for current semiconductor package. Due to lead frame with long inner leads and outer leads, such conventional lead-frame assembly package can not applied to chip scale package and low profile package. Thus leadless assembly package, such as Quad-Flat-Non-lead Package which is initially developed by Matsushita, is wildly provided in the semiconductor package industry to reduce the size of the assembly package in the recent years. Referring to FIG. 1, a conventional leadless assembly package is disclosed. The leadless semiconductor package 100 mainly comprises a leadless lead-frame 110 such as a copper lead-frame, a chip 120, an adhesive 130, a plurality of conductive wires 140 and an encapsulation 150. Therein, the leadless lead-frame 110 has a chip paddle 112 and a plurality of leads 114 surrounding the chip paddle 112; and the chip paddle 112 comprises a chip disposal area 112a and a grounding area 112b; and the chip 120 is disposed above the chip disposal area 112a through an adhesive 130, such as silver paste, connecting the back surface 122 of the chip 120 and the chip disposal area 112a. Moreover, the chip 120 further has an active surface 124 and a plurality of bonding pads 126 formed on the active surface 124; and the chip 120 is electrically connected to the top 114a of the lead 114 and the grounding area 112b of the chip paddle 112 through the conductive wires 140, such as gold wires. And the encapsulation 150, such as molding compound, encapsulates the leadless lead-frame 110, the chip 120 and the conductive wires 130 and exposes the bottom 112c of the chip pad 112 and the bottom 114b of the leads 114 so as to form a plurality of electrical terminals to connect to external electronic devices through surface mount technology (SMT).
As mentioned above, the chip paddle 112 of said leadless semiconductor package 100 exposes the bottom 112c and 114b of the leadless semiconductor package 100 so as to further improve the thermal performance of said leadless semiconductor package. Furthermore, due to the short leads, the impedance will be lower. Accordingly, the leadless semiconductor package is especially adapted to the assembly package with high-frequency devices, which are performed at the frequency from 10 GHz to 100 GHz, enclosed therein. In such a manner, such leadless semiconductor package has low cost and competitive price. Therefore the leadless semiconductor package is adapted to cell phone, personal digital application (PDA), digital camera and information application (IA).
As can be seen, the reliability of said leadless semiconductor package is relied upon the performance of the attachment of the encapsulation 150 to the lead frame 110. Namely, when the encapsulation 150 is able to well encapsulate the lead frame 110, the leadless semiconductor package will have a better reliability. However, usually the reliability of the leadless semiconductor package is lowered due to the change of working temperature. Namely, the encapsulation 150 is usually caused to be separated from the lead frame 110 upon the difference of the thermal coefficient of expansion of the lead frame 110 from that of the encapsulation 150 and the changes of the working temperature. Besides, referring to FIG. 1 again, an adhesive 130 is interposed between the chip disposal area 112a and the back surface 122 of the chip 120 to have the chip 120 securely attached to the chip paddle 112. However, when the adhesive 130 is an epoxy resin or a silver paste and the size of the chip 120 is slightly smaller than the size of the chip paddle 112, the adhesive 130 is easily to flash over and flow over the grounding area 112b. Specifically, when the distance between the periphery 128 of the chip 120 and the periphery of the chip paddle 112, namely the width D of the grounding area 112b, is not greater than six (6) mils, exceeding adhesive will more easily flash over and flow over the grounding area 112b so that the conductive wires 130 will not be well bonded to the grounding area 112b and the reliability of said package will be lowered.
Consequently, providing another leadless semiconductor package to solve the mentioned-above disadvantages is the most important task in this invention.